Three Phase Seven-level Triple Voltage Booster Switched-Capacitors based Multilevel Inverter with Mi by IRJET Journal

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Three Phase Seven-level Triple Voltage Booster Switched-Capacitors based Multilevel Inverter with Minimum Components

Vikram Singh Sehmi1 , Dr. Nagendra Tripathi2

1M.Tech. Student, Department of Electrical Engineering, Bhilai Institute of Technology, Bhilai (C.G.), India

2Professor, Department of Electrical Engineering, Bhilai Institute of Technology, Bhilai (C.G.), India ***

Abstract: This research proposes an economically feasible 3-phase triple-gain switched-capacitor (SC) multilevel inverter (MLI) configuration. The proposed structure has one source and uses the fewest switching components possible to produce an output voltage waveform with seven levels from line to line. The newly proposed SCMLI configuration features a built-in capacitor voltage balancing capability and uses two switching capacitors per phase leg. Level shift pulse width modulation approach, operating theory, and structural description have all been discussed. To demonstrate the merits of the proposed work with the existing topologies, a fair comparison study has been provided. The simulation results show that the proposed SCMLI configuration is feasible and has been verified theoretically.

Keywords: Three Phase Multilevel Inverter; Seven Level MLI; Economically Feasible Inverter Design, SCMLI.

1. Introduction

Thepopulationandindustrializationareexpandingquickly,whichincreasestheusageoftraditionalenergysources andgreenhousegasemissions[1].Therehasbeenalotoffocusonsustainableenergysourcesasawaytoslowdownthe rateatwhichconventionalenergysourcesareusedup.However,electricityisproducedbyavarietyofrenewableenergy sources, including solar photovoltaic, wind, and fuel cells. Solar and wind are the most widely used renewable energy sourcesduetotheiraccessibility,environmentalfriendliness,andimprovementsinpowersemiconductortechnology Due tothe relatively low output power from this source, it will not meet the requirements for power qualityfor applications likeelectricandfuel cellvehicles,gridconnections,andindustries.Asa result,a transformeror boostconvertermustbe usedtoincreasetheoutputvoltage.Theuseofthetransformermakesthesystembigandexpensive. Anextensiveamount ofstudyhasbeendoneontheconvertertoincreasetheoutputvoltage. Amongtheseconverters,multilevelinvertersare essential for power conversion owing to improved power quality, enhanced performance, and low, medium, and highpowerapplications.

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ThecascadedH-bride(CHB),theflyingcapacitor(FC),andtheneutralpointclamped(NPC)inverterarethethreeprimary topologies of the conventional multilevel inverter [2] Every topology has advantages and disadvantages. A modularity feature,forexample,ispresentinthecommonCHB. However,theneedforisolatedDCsourcesisitsprincipaldrawback. ForNPCandFCtopologies,theavailabilityofclampingdiodesandcapacitors,respectively,andtheaccompanyingvoltage balance concerns provide a difficult problem. The uses of conventional inverters are constrained by these undesirable characteristics.Inthiscontext,researchhasconcentratedondesigningMLIstopologiesthatusethefewestpossiblepower electronic components while still producing improved voltage waveforms [3, 4]. The ability to increase voltage is a key worry with such topologies, though. Researchers from all over the world have looked into the switched capacitor (SC) concept as a way to lessen the aforementioned limit. Such MLIs structures based on SC display exceptional voltage boostingcapabilities,capacitorself-voltagebalancing,andagreaternumberoflevelsduetoitsmodularitycharacteristic. BasedontheSCprinciple,thetopologies[5-7]havepropertiesofmodularity.Thesedesignsare,however,constrainedby highvoltagestressonthepowerswitchingdevices.Abasiccellunitcangenerateanoutputvoltagewaveformwithseven levelsusingthetopologydescribedin[8].Despitehavingasymmetricalvoltagesource,thetopologyislessdesirableand more expensive due to the need for numerous sources and a polarity generator. The gain is lower and there are more switching components in the architecture [9-11]. Another seven-level topology [12] also employs more switching components while gaining less than unity. The arrangement [13] has seven levels and three times the input voltage source's voltage boosting capabilities, furthermore, its drawback is that it causes undesirable voltage stress across the switches Voltageboostingisnotpossiblewiththedesignedstructureforthetopologiesshownin[14-17].Aninnovative ANPCinverterthatmaygeneratemaximumvoltagelevelswhilemaintainingunityorahighervoltagegainwasexploredin the structures in [18–21]. Moreover, the overall component count is decreased, and complex balancing controls are not necessary. In [22], a unique SC T-type inverter is presented that soft-charges its integrated switching capacitors to www.irjet.net p-ISSN:

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minimizecurrent spikes. A nine-level single-sourcedesign builton theSC principle issuggested inthearticle[23],but it has fewer components than traditional topologies. The amount of parts required to reach the appropriate level is still considerable, though. In order to accommodate the extra switches, driver circuitry must be added, which raises the system's cost and increases power loss. Neutral Point Clamped Inverters (NPCI), which generate three-level alternating current(AC)outputinasinglestage,arerecommendedforusageinboostingDCvoltagetotherequiredlevel[24,25].In thearticle[26],designingasinglephasehybridmultilevelinverterforastandalonesystemthatproducesthreelevelsofTtypelegandthreelevelsofdiodeclampedlegusingasymmetricalvoltageinputsourcesisdiscussed.

The majority of topologies, it has been shown through a survey of the literature, have a number of demerits, including increased power devices, high voltage stress across the switches, low voltage gain, and absence of enhancing ability Therefore, the ideasin the aforementioned statements have been employed to developthe alternative SC-based inverter configuration that isdiscussed in theproposed work Thefollowingare the primarycharacteristicsof the recommended topology:

a) Themagnitudeofthevoltageboostingcapabilityisthree.

b) Theinbuiltabilityofcapacitorstobalancetheirvoltages.

c) Itdecreasedthenumberofswitchingcomponents.

d) Useofasinglesource,

e) Onlyabout50%ofswitchingpartsarefunctionalatanyvoltagelevel.

2. The Proposed 3-Ф SCMLI Topology A. Circuit Description

The3-ФSCMLIstructuraldesignisdepictedinFigure1.Sixpowerswitches(SXi i.e.,1,2,...,6)areusedineachphase leg,togetherwithapowerdiode(DX),twocapacitors(CX1 andCX2),andasingleDCsource,whereX thephase(R,Y,B). Any renewable energy source or battery can provide power to this voltage source. The proposed SCMLI can produce a seven-levelvoltagewaveformacrosstheloadendswhentheline-to-linevoltageistakenintoaccount(0,+1VDC,+2VDC,and +3VDC),butwhenthepolevoltageVRO istakenintoaccount,theproposed structurecanonlyproducefourlevels: 0,±VDC, ±2VDC,and±3VDC.All theusedpower switcheshavepeak inversevoltages(PIV) equal to thatoftheinputsupply voltage exceptforSX5 andSX6.Theproposedstructuredemonstratessymmetryinallthreephases,thusfocusingononlyonephase leg(R)willhelpyoubetterunderstandtheanalysis.Table1enlistsalltheappropriateswitchingmodes Inthementioned table, ‘1’ and ‘0’ stand for the switches ON and OFF states, respectively. Capacitor charging and discharging are representedbytheletters‘C’and‘D’

B. Different operational modes of the proposed topology

This section explains the basic operation of single phase. The remaining two phases can be analysed similarly The techniquesoutlinedbelowcanbeusedtocharacterisePhaseR:

VDC CR2 DR SR6 SR2 SR3 CR1 SR5 + SR1 SR4 + R CY2 DY SY6 SY2 SY3 CY1 SY5 + SY1 SY4 + Y CB2 DB SB6 SB2 SB3 CB1 SB5 + SB1 SB4 + B

Fig.1. Proposed3-ФSCMLItopology

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Mode 1: In this mode, two switches are operated, causing output voltage levels across the R and n terminals to be zero(seeTable1).ThecapacitorCR1ischargedto VDC,whosemagnitudeisequivalenttotheinputvoltagesource,asa result of the switch SR2 beingactivated. Fig. 2a depictstheanalogouscircuit for this device. The capacitor's charging pathisdepictedhereinblue,whilethecurrentflowingthroughtheloadterminalsisshowninredlines

Mode 2: Inthismodeofoperation,theswitchesSR2 andSR5 areturnedontoprovidethisvoltagelevelandtocharge thecapacitorsCR1 toalevelthatisequaltotheDClinksource,asdepictedinFig.2b.

Mode 3: The proposed topology generates a voltage level that is double the input voltage supply magnitude in this modeofoperation(2VDC).ThefollowingpowerswitchesSR1,SR4,andSR5areturningon,whichconnectscapacitorCR1 inserieswiththesourceoftheinputvoltageandchargescapacitorCR2 to2VDC.Asaresult,theloadterminalsgenerate theoutputlevelof2VDC,asshowninFig.2c.

Mode 4: Inthismode,thesourceoftheinputvoltageislinkedinserieswithbothcapacitors: CR1 and CR2, output voltage of 3VDC is measuredacross the load terminals. The mode 4operation for the indicated structure is shown in Fig.

ofoperationofthepolevoltage(a)VRO(t)=0

2d.

Mode Activeswitch VRO(t) Capacitorseffect SR1 SR2 SR3 SR4 SR5 SR6 CR1 CR2 I 0 1 0 0 0 1 0 CII 0 1 0 0 1 0 1VDC CIII 1 0 0 1 1 0 2VDC D C IV 0 0 1 0 1 0 3VDC D D

(b)VRO(t)=+1VDC(c) VRO(t)=+2VDC (d)VRO(t)=+3VDC VDC CR2 DR SR6 SR2 SR3 CR1 SR5 + SR1 SR4 + R O + (a) VDC CR2 DR SR6 SR2 SR3 CR1 SR5 + SR1 SR4 + R O + VRO(t) (b) VDC CR2 DR SR6 SR2 SR3 CR1 SR5 + SR1 SR4 + R O + VRO(t) (c) VDC CR2 DR SR6 SR2 SR3 CR1 SR5 + SR1 SR4 + R O + VRO(t) (d)

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Table 1 Switchingstatesforpolevoltageofphaseleg‘R’

Fig.

2. Showsthedifferentmodes

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3. Switching methodology

Theoretically, high frequency switching techniques such as: multicarrier pulse with modulation, space vector pulse width modulation, etc. or low switching frequency schemes such as: active harmonic elimination, selective harmonic elimination, etc. can be used to modulate the proposed SCMLI configuration with the appropriate adaption [21–23]. A multicarrierPWMmethodasdescribedin[24]isusedinthispapertodemonstratehowthesuggestedtopologyoperates. Figure 3 depicts the scheme, while as carriers, six 2 KHz-frequency triangle waveforms are used. They are set up in an opposingphaseconfiguration[25].

Thereferencesignalisasinusoidalwaveformat50Hzfrequencywitharandomlyselectedmodulationindexof0.95. Thecarriersignalsandthe referencesignal are continuouslycompared.Comparatorsoutput‘1’forcarriersignalsabove the zero reference if the reference is greater than the associated carriers and ‘0’ otherwise. Comparators output ‘0’ for carrier signals below the zero reference if the reference is bigger than the associated carriers, and ‘-1’ otherwise. The output signals from the comparator are combined to produce an aggregate signal (t). Furthermore, in order to generate switchingpulsesfromsignalaone-to-onerelationshipbetweenthelevelspresentinsignala(t)(aggregatedsignal)andthe levelsdesiredintheoutputwaveformisused. Thisisdonebycomparingthesignala(t)totheconstants.Thesignalsthus acquired are applied to power switches succeeding to the level utilizing the mapping depicted in Fig. 3 to control the switches.

4. Simulation results and discussion

TheproposedstructurehasbeenvalidatedusingtheMATLAB/Simulink platformtoconfirmthebroadconceptual concept. Usingthe techniqueoutlinedinthe sectionabove,highfrequencycarrier signalshave been carefullychosen for modulation.Table2liststhecircuitdesignparametersusedontheSimulinkplatformfortheverificationoftheproposed SCMLIstructure.

The theoretical idea of the proposed topology is supported by simulation outcomes. Fig. 4 and Fig.5 show the outcomesofthesimulationwithRL-load.InFig.4a,thepolevoltageisshownwithfourequalstepsizes(0,+ 100V,+200 V,+300V).Fig.4bshowsthethree-phaselinevoltage.Linevoltagehassevenlevels(0,100V,200V,300V),ascanbeseen from the waveform. The resistive-inductive load current under step-change load conditions is shown in Fig. 5a. Fig. 5b illustratestheimpactoftheloadchangeonlinevoltage,linecurrent,andcapacitorvoltageforphaseRforeasieranalysis. Thisrevealsthatevenwhentheloadvaries,thecapacitorretainsitsnaturalbalanceandthatthelinevoltage'smagnitude isunaffected.

Carriersignal abovethezero reference Carriersignal belowthezero reference Sinusoidal referencesignal + + 1 0 0 -1 == 0 == 1 == 2 == 3 == -3 == -2 == -1 0 3Vdc -3Vdc Vdc 2Vdc -Vdc -2Vdc a(t) Mapped levelat output terminals

Fig.3. Switchingschemefortheproposed3-ФSCMLI

Table 2 Simulationparameters

InputDCsource(VDC) 100V

Outputfrequency(f) 50Hz

Carrierfrequency(cx(t)) 2kHz

Resistive-InductiveLoad R=50Ω,L=80mH

Capacitors(CXi) CX1=6000 ,CX2=4700

PowerSwitches IGBTs

Modulationindex(Ma) 0.95

ThevoltagestressesovervariousswitchesareshowninFigure6a.WhentheR-LloadofR=50, L=80mHistaken into account, the FFT analysis of VRY yields the highest magnitude of the fundamental voltage of 171.6V with 31.08% of total harmonic distortion(THD),asshown inFig.6b. Similarto this,the FFTanalysisof iRY yields a fundamental current peakmagnitudeof1.775Awith1.45%THDasshowninFig.6c Itcapturessteady-statevaluesof100Vand96.5VoverCx1 andCx2,respectively.ItalsomentionsthatCx1 andCx2 havepeak-to-peakripplevaluesofabout2.5Vand2V,respectively.

Simulationsresultsforproposed3-ФSCMLItopology:(a)polevoltage,(b)linevoltages

Parameter Specification

Time [s] 0.26 0.28 0.3 0.32 0.34 0 300 200 0 200 300 300 0 200 P o l e V o l t a g e [ V ] VRn VYn VBn (a) 0.26 0.28 0.3 0.32 0.34 Time [s] 300 -300 0 -300 300 0 300 0 -300 VRY VYB VBR L i n e V o l t a g e [ V ] (b)

Fig.4.

(b)linevoltage,loadcurrentandvoltageacrosscapacitors

International Research Journal of Engineering and Technology (IRJET) e-ISSN:2395-0056 Volume: 10 Issue: 04 | Apr 2023 www.irjet.net p-ISSN:2395-0072 © 2023, IRJET | Impact Factor value: 8.226 | ISO 9001:2008 Certified Journal | Page1015 Time [s] L o a d C u r r e n t [ A ] 0.26 0.28 0.3 0.32 0.34 0 4 -6 2 -2 6 -4 IR IY IB (a) Time [s] I R Y [ A ] 0.26 0.28 0.3 0.32 0.34 -6 6 190 90 200 300 0 -300 V R Y [ V ] V C R 1 [ V ] V C R 2 [ V ] 0 110 (b)

Fig.5. Simulationsresults:(a)loadcurrent

International Research Journal of Engineering and Technology (IRJET) e-ISSN:2395-0056 Volume: 10 Issue: 04 | Apr 2023 www.irjet.net p-ISSN:2395-0072 © 2023, IRJET | Impact Factor value: 8.226 | ISO 9001:2008 Certified Journal | Page1016 SR1 SR2 SR3 SR4 100 100 100 0 0 0 0 0.26 0.28 0.3 0.32 0.34 S w i t c h V o l t a g e [ V ] 100 Time [s] (a) (b) (c)

Fig. 6. Simulationresultsof(a)voltagestressacrossswitches(SR1,SR2,SR3 andSR4),(b)VoltagewaveformFFT analysis,(c)CurrentwaveformFFTanalysis

5. Comparison of Proposed SCMLI with existing 3-Ф MLI topologies

The primary goal of the presentedtopology is to produce the highestnumber of output voltage levels with the fewest possible power devicesand capacitors at the lowest possible cost The Component to Level Factor (FC/L) and the CostFunction(CF)aretwovariablesthatquantify themeritsofthesuggestedtopologyinthiscontext(CF).Theequation belowdefinesthecostfunctionandthefactorcomponenttolevelfactor(FC/L).

And,

Here,thenotationsrepresentnumberofpowerswitches= ,capacitors= ,auxiliarydiodes= NAD,sources= , numberofpolevoltagelevel= ,driverunits= ,polevoltagelevels= NL1,bodydiodes = NBD,andline-to-linevoltage levels= NL2.αistheweightfactorandnumberoftheinductors= NI.

Foracertainnumberofpolevoltagelevels,Table3includescomponentcount,costfunction,totalstandingvoltage, andvoltagegainthatcomparestheproposedtopologytotheexisting3-ФSCMLIstructures.MultipleisolatedDCsources arepresentinthetopologiesdescribedinRef.[14,15,20]toraisethevoltagelevel.Thetopologyinreference[12,14,15, 17,20]hasapoorabilitytoincrease.Despitehavingthepotentialtoraisevoltage,thetopologiesinref[9–11]areonly1.5 times as effective as the proposed one. Additionally, the proposed topology has a lower CF than recent topologies. The leastexpensivetopology,however,is[12,17].Itrequiresaboostingcircuit,whichaddsexpenseandcomplexity.

(1)

(2)

Sl.no NL1 NL2 NSW NS NAD Nl NBD NDri NC TSVpu FC/L MBV Gain Boosting ability CF/gain [9] 4 7 10 1 - - 10 9 4 6 8.5 1 1.5 Yes 6.5 [10] 4 7 9 1 - - 9 8 3 5.33 7.5 1 1.5 Yes 5.72 [11] 4 7 10 1 - - 10 9 3 5.33 8.25 1 1.5 Yes 6.22 [12] 4 7 8 1 - - 8 8 3 4 7 1 0.75 No 10.33 [14] 3 5 4 2 - - 4 4 - 5 4.66 2 1 No 11.33 [15] 4 7 6 4 8 - 4 6 - 17.33 7 3 0.75 No 23.73 [17] 4 7 8 1 - - 8 8 4 5.5 7.25 1 1 No 8.387 [20] 3 5 4 2 - - 4 4 - 5 4.66 2 1 No 11.33 [P] 4 7 6 1 1 - 6 6 2 4 5.5 3 3 Yes 2.08 TSV:TotalStandingVoltage, MBV:MaximumBlockingVoltage

Table 3 Comparison of proposed SCMLI (P) with the recent MLI topologies

6. Conclusion

Athree-phaseSCinverterthatboostsvoltageeffectivelyisdescribedinthisarticle.Thesuggesteddesignisnotable for having the fewest active and passive switching components per level, lower cost function values, and self-balanced capacitor voltage. Due to these aspects, it is envisaged that the suggested topology will mostly be employed for solar panels,fuelcells,andelectriccars.Thepresentedmodulesynthesisessevenlevelsusingpowerswitchesthatareallrated at the same voltage as the input dc source. The proposed module is determined and analyzed and its MATLAB/Simulink simulation is described in this paper. A fair comparison of the newly presented SCMLI structure with other switched capacitors-based topologies further demonstrates its superior performance and competence in terms of semiconductor requirements.

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