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International Research Journal of Engineering and Technology (IRJET)

e-ISSN: 2395-0056

Volume: 10 Issue: 04 | Apr 2023

p-ISSN: 2395-0072

www.irjet.net

DESIGN OF POWER EFFICIENT PRIORITY ENCODER D. Gopikrishna1, G. Chandrashekar2, Dr. D. Asha Devi3 1,2B. Tech Scholars, Department of Electronics and Communication Engineering, SNIST, Hyderabad-501301, India 3 Professor, Department of Electronics and Communication Engineering, SNIST, Hyderabad- 501301, India

---------------------------------------------------------------------***--------------------------------------------------------------------Abstract -This paper endeavors to design power efficient 2. LITERATURE SURVEY priority encoder involving virtuoso software in cadence automation tool. The IC industry's primary concern is conserving energy. In this project, one such effort is the design of a 4:3 priority encoder. A novel CMOS-based design for a lowpower 4:3 Priority Encoder is presented in this project. The power consumption of the proposed designs is lower than that of standard adiabatic logic designs. At 180nm CMOS technology, the simulation is carried out using Virtuoso software. Drive simulation and LVS-clean layout of ICs and packages from a single schematic are both features of the Cadence Virtuoso System Design Platform, a holistic, systembased solution. There are two significant flows: execution and evaluation.

Key Words: Priority Encoder, Virtuoso

2.1. Existing Model Power-saving priority encoders are available in a variety of designs. A few examples include: 1.Parallel Need Encoder: In this model, all input signals are compared in parallel and the signal with the highest priority is chosen. Despite its speed and simplicity, this model may use more power due to the use of numerous comparators. 2.Sequential Need Encoder: The input signals are compared in this model, starting with the signal with the highest priority. The number of comparators required decreases as a result, but the propagation delay may increase.

CMOS

technology, Cadence , IC .

3. Encoder from Binary to Priority: Priority outputs are generated from binary inputs using this model. It has a faster response time than the sequential model and uses fewer comparators than the parallel model. However, it might use more power and require more logic gates.

1.INTRODUCTION Planning a power-effective need mail encoder in Virtuoso programming in rhythm is a complicated cycle that includes a few plan stages. A digital circuit known as a priority mail encoder prioritizes incoming data according to predetermined criteria. In this plan, we expect to make a power-proficient need mail encoder involving Virtuoso programming in rhythm, a famous electronic plan computerization device.

4. Dynamic Priority Encryption: This model purposes dynamic rationale doors, like domino rationale, to lessen power utilization. It has a quicker reaction time than different models yet requires cautious timing examination and can be helpless to commotion.

Moving on to the layout design, where we will create a physical layout of the circuit, we will verify the circuit's functionality. The design configuration stage is basic for guaranteeing that the circuit meets the ideal exhibition and usefulness necessities while limiting power utilization. Finally, in order to ensure that the circuit satisfies the power efficiency requirements, we will carry out a post-layout simulation and examine its power consumption. We will use a variety of optimization techniques throughout the design process to make sure the circuit meets the specifications and uses as little power as possible. Virtuoso software Cadence requires a thorough understanding of digital circuit design, optimization methods, and power management principles to design a power-efficient priority mail encoder. Virtuoso programming Rhythm gives a complete arrangement of instruments that can help us plan and recreate complex computerized circuits and streamline them for power utilization

Impact Factor value: 8.226

2.2. Proposed Model Virtuoso software was used to design a priority encoder that uses less power. To cut down on power consumption, techniques like clock gating, voltage scaling, and transistor sizing were used to improve the design. To make use of less chip space, the priority encoder was implemented using static CMOS logic with fewer transistors. Because it is compatible with a variety of input signal and output formats, the proposed design is adaptable to a variety of applications. Through simulations, the priority encoder's performance was confirmed, with faster response times and shorter propagation delays compared to conventional designs. In general, the power-efficient priority encoder design that has been proposed offers a number of advantages in terms of power consumption, performance, and area, making it suitable for applications requiring low power and limited space.

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