International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 12 Issue: 04 | Apr 2025
p-ISSN: 2395-0072
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Double fault tolerant architecture design for digital adder Kunapaneni Vasavi1, Swarna Latha2, Sangepu Manisha 3, Nuthakki Sujith4, Kasu hari krishna Reddy5 1Student & AMRITA SAI INSTITUTE OF SCIENCE AND TECHNOLOGY
2Assistant Professor & AMRITA SAI INSTITUTE OF SCIENCE AND TECHNOLOGY 3Student & AMRITA SAI INSTITUTE OF SCIENCE AND TECHNOLOGY 4Student & AMRITA SAI INSTITUTE OF SCIENCE AND TECHNOLOGY 5Student & AMRITA SAI INSTITUTE OF SCIENCE AND TECHNOLOGY
---------------------------------------------------------------------***--------------------------------------------------------------------Abstract 1. INTRODUCTION In the rapidly evolving domain of digital electronics and embedded systems, the demand for reliable, error-resilient arithmetic circuits has become critical, especially for applications in aerospace, biomedical systems, cryptography, and safety-critical industrial automation. One of the most fundamental and frequently used digital components is the binary adder, which plays a crucial role in various computing operations. However, traditional adder architectures are prone to hardware faults such as bit-flips, stuck-at faults, and transient errors caused by power fluctuations or radiation, particularly in harsh environments. In light of these vulnerabilities, the present research introduces a novel Double Fault Tolerant Architecture Design for Digital Adders, aimed at enhancing computational reliability and system integrity through fault-resilient design techniques.
In the realm of digital electronics, ensuring system reliability is a critical concern, particularly in applications where failure is not an option, such as aerospace, medical devices, nuclear control systems, and automotive electronics. The rising demand for faulttolerant systems has encouraged the exploration of architectures that can continue to operate correctly even when hardware faults occur. One of the fundamental building blocks in digital systems is the adder, a key component of the Arithmetic Logic Unit (ALU). As such, its reliability directly impacts the performance and correctness of the overall system. In this context, the development of a double fault tolerant architecture for a digital adder holds significant importance. Fault tolerance is the ability of a system to continue operating properly in the event of the failure of one or more of its components. Traditional fault-tolerant systems are typically designed to withstand a single fault. However, with the continuous scaling of transistors in Very Large Scale Integration (VLSI) and the rise of soft errors caused by environmental radiation, multiple simultaneous faults have become increasingly probable. Therefore, systems capable of tolerating double faults are essential for maintaining robust functionality.
The proposed architecture is designed using Verilog Hardware Description Language (HDL), simulating the behavior of a 4-bit binary adder under a double fault tolerance mechanism. The system integrates a layered approach using modular redundancy, fault masking, and selective multiplexer-based reconfiguration to mitigate the effects of both permanent and transient faults. The core components include multiple layers of multiplexers, fault-tolerant full adder units, dynamic mux-select signal generation units, and a custom-designed test pattern generator. These elements work in synergy to dynamically reconfigure the data path, ensuring uninterrupted and accurate output even in the presence of two simultaneous faults.
The digital adder is one of the most used components in any digital system. From simple data processing to complex computational tasks, adders serve as the core of arithmetic operations. Consequently, designing fault-tolerant adders that ensure reliable and accurate operation under fault conditions is a necessity in modern digital designs. A double fault tolerant digital adder aims to produce correct outputs despite the occurrence of up to two simultaneous faults in its circuitry. This approach not only enhances the system’s dependability but also extends its usability in missioncritical applications where safety and accuracy are paramount.
Keywords: Fault Tolerant Architecture ,Digital Adder , Double Fault Tolerance ,Verilog HDL ,Fault Masking , Redundancy ,Arithmetic Logic Unit (ALU) ,Hardware Reliability ,Multiplexer-Based Design ,Safety-Critical Applications
The conventional methods to achieve fault tolerance include Triple Modular Redundancy (TMR),
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