Design and Synthesis of Majority Logic Gate Based MAC Units with FPGA and ASIC Evaluation

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

Design and Synthesis of Majority Logic Gate Based MAC Units with FPGA and ASIC Evaluation

B. Haritha Lakshmi1 , D. Dinesh Vardhan2 , P. Padma Sarojini3,K. Ashwin Vaibhav Datta4 , M. K. S. Krishna Adithya5 , Punnam Nagaraju6

12345 B. Tech Students, 6 Assistant Professor, Department of Electronics and Communication Technology, S. V. E. C, Tadepalligudem, Andhra Pradesh, India

Abstract - Inthisproject,4×4and8×8Multiply-Accumulate (MAC) units based on Majority Logic Gates (MLGs) are designedandevaluated.Whilepartialproductsareproduced using traditional logic, MLG is utilized in the arithmetic phase of the suggested design, namely in the full adders and multiplier reduction path. In order to confirm functionality andexamineresourceusage,timing,andpower,theMACunits wereinitiallysimulatedandsynthesizedonFPGAusingXilinx Vivado. The same MAC designs were functionally validatedand synthesized using Ubuntu, Yosys, OpenLane, and OpenROAD, andtheirarea,latency,andpowerweremeasuredinorder to better assess the design in an ASIC context. After the initial development and analysis of the 4×4 MLG MAC, the same designconceptwasexpandedtoan8×8MLGMAC.Functional verification verified that both setups' multiply-andaccumulateoperations were accurate. The project highlights the trade-offs between MAC size, area, delay, and power and shows that MLG-based arithmetic can be implemented and studied on both FPGA and ASIC platforms.

KeyWords: Multiply-Accumulate (MAC) units1, Majority Logic Gates (MLGs)2, FPGA3, ASIC4, MLG-based arithmetic5etc.

1.INTRODUCTION

Multiply-Accumulate (MAC) units are essential parts of contemporarydigitalsystemsandarewidelyemployed in machine learning, image processing, and digital signal processing. The MAC unit's efficiency in terms of space, latency,andpowerconsumptionhasasignificantimpacton thesesystems'performance.Booleanlogic-basedarithmetic units,whichrelyonnumerouslogicgateslikeAND,OR,and XOR, are commonly used to create conventional MAC architectures.Particularlyasthedesigngrows,thisresultsin higherswitchingactivity,moresophisticatedcircuitry,and ultimatelyhigherpowerconsumption.

In this work, Majority Logic Gate (MLG)-based designisintegratedintothearithmeticsectionoftheMAC unit, specifically in the design of full adders and in the multiplierreductionpath,whilepartialproductgenerationis retainedusingconventionallogicforreliability.MLG-based

design offers a promising solution to these limitations. Majority logic enables compact realization of arithmetic functions by reducing the number of logic levels and simplifyingcarrypropagationinadders.

Inordertoinvestigatescalabilityandperformance trade-offs, the suggested MAC designs are constructed in both 4×4 and 8×8 configurations. In order to assess the designs' performance on various platforms, they are functionally validated and synthesized utilizing FPGA and ASICdesignprocedures.WhileYosyswithSky130standard cell libraries is used for ASIC synthesis and OpenROAD is used for area, delay, and power analysis, Xilinx Vivado is used for FPGA implementation to study resource consumption,timing,andpower.Theoutcomesshowthat MLG-based MAC design is feasible and shed light on the trade-offsbetweenpowerconsumption,performance,and designsize.

2. PROPOSED ARCHITECTURE

The design of Majority Logic Gate (MLG)-based MultiplyAccumulate (MAC) units in 4×4 and 8×8 configurations is shown in the proposed work. By adding majority logic to crucialarithmeticcomponents,thearchitectureisdesignedto increase computing efficiency while preserving reliability throughtraditionalpartialproductgeneration.

2.1 Overall MAC Structure

Thethreeprimaryphasesoftheoverallarchitectureare accumulation, reduction and addition, and partial product creation. An array-based structure is used to perform the multiplicationoperation,andaregister-basedaccumulatoris usedtoaggregatetheresultoveraseriesofclockcycles.

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

Table -1: TruthtableofMajorityLogicGate

Fig -1:OverallMACStructure

2.2 Majority Logic Gate Fundamentals

TheMajorityLogicGate(MLG)isafundamentalbuilding blockusedintheproposeddesign.A3-inputMLGproduces anoutputbasedonthemajorityofitsinputsandisdefined as:

F=AB+BC+CA

ThesymbolandtruthtableoftheMLGareshowninFig.2 andTable1,respectively.

Fig -2:MajorityLogicGateSymbol

2.3 Partial Product Generation

The suggested architecture uses traditional ANDbased logic to build partial products. A matrix of partial productsiscreatedforaN ×NMACbyANDingeachbitof themultiplicandwitheachbitofthemultiplier.Byavoiding approximationinthemostcrucialpartofthecomputation, thismethodguaranteesaccuracyandsimplicityinthefirst multiplicationstage.

2.4 MLG-Based Reduction and Addition

TheusageofMajorityLogicGatesinthearithmetic portion, specifically in Full Adder Design and Multiplier Reduction Path, is the main contribution of the suggested architecture.TheemploymentofMajorityLogicGatesinthe arithmeticarea,specificallyin:

Cout=Majority(A,B,Cin) and majority logic and inversion are combined to determinethesum.ComparedtotraditionalXOR-basedfull adders, this lowers the number of logic levels and streamlinescarrypropagation.

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

AnetworkofMLG-basedfulladdersisusedinthe multiplier reduction path to aggregate several partial products. By effectively compressing the partial product matrix,thisreductionstagereducesswitchingactivityand logicdepth.Theconceptreduceshardwarecomplexityand improves power efficiency by substituting MLG-based implementationsfortraditionaladderarchitectures.

2.5 Accumulation Unit

A register that holds the MAC operation's intermediateresultisusedtoimplementtheaccumulation stage. The multiplier's output is added to the previously accumulated value at each clock cycle. A synchronous register-based structure is used to do this, allowing multiplicationresultstobeaccumulatedsequentially.

2.6 4 × 4 MAC Architecture

Thebasedesignisa4×4MACunit.Itincludes:

 4-bitinputsB[3:0]andA[3:0]

 UsingANDlogictogenerateapartialproduct

 ReductionwithcompleteaddersbasedonMLG

 Anoutputofan8-bitproduct

 Anaccumulatorbasedonregisters

This setup is used to examine the MLG-based approach'sperformanceintermsofarea,delay,andpower aswellastoverifythatitiscorrect.

2.7 8 × 8 MAC Architecture

Byexpandingthesamedesignideas,thesuggested architectureisexpandedtoan8×8MACunit.The8×8MAC consistsof:

 A[7:0]andB[7:0]are8-bitinputs.

 Abiggermatrixofpartialproducts

 AlargerreductionnetworkbasedonMLG

 Theoutcomeofa16-bitmultiplication

 Forsequentialaddition,abroaderaccumulator

By methodically increasing the number of partial products and matching reduction stages while preserving the MLG-based adder structure, the architecture is made scalable.Thismakesitpossibletoexaminehowthedesign respondstolargeroperandsizes,especiallywithregardto trade-offsbetweenarea,latency,andpower.

2.8 Design Significance

Forarithmeticoperations,thesuggestedMLG-based MACarchitectureprovidesascalableandeffectivesolution. The design achieves regulated power behavior and decreasedlogiccomplexitybyincorporatingmajoritylogic into crucial computing stages, making it appropriate for contemporaryVLSIapplications.

3. Design Methodology

BothFPGAandASICdesignflowswereusedinthedesign, verification,andevaluationofthesuggestedMajorityLogic Gate (MLG)-based MAC designs in order to assess their performance on various platforms. RTL design, functional verification,synthesis,andperformanceanalysisareallpart ofthetechnique.

3.1 RTL Design and Functional Verification

VerilogHDLwasusedtodescribetheMACunitsin both4×4and8×8designs.Thedesignconsistsofmodulesfor accumulation,multiplierreduction,MLG-basedfulladders, and partial product creation. By applying several input combinationsandtrackingthecumulativeoutputoverclock cycles, a testbench was created to confirm the MAC unit's operation.

The accuracy of the multiply-accumulate process was confirmed through functional verification utilizing simulation tools. To guarantee correct synchronization between input operands, multiplication outcomes, and accumulation behavior, the simulation results were examinedusingwaveformviewers.

3.2 FPGA Synthesis and Analysis

The suggested MAC architectures were created using Xilinx Vivado in order to assess the idea in an FPGA environment. Key performance metrics, including the following,wereobtainedbysynthesizingandimplementing theRTLdesign:

 LogicUtilization(LUTs)

 RegisterUtilization

 Timingperformance

 Consumptionofpower

Aninitialevaluationofthedesign'sresourceusageand operational effectiveness is given by the FPGA synthesis results. Additionally, this stage verifies that the design is bothsynthesizableforhardwarerealizationandfunctionally valid.

3.3 ASIC Synthesis and Using Yosys

Yosys is an open-source synthesis program that was usedtocreatethesameRTLdesignforASICevaluation.RTLto-gate-level synthesis was used to process the Verilog design, and the Sky130 standard cell library was used to carryouttechnologymapping.Thesynthesisflowconsists of:

 ReadingVerilogRTLfiles

 Performinglogicsynthesis

International Research

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

 MappingtoSky130standardcells

 Generatingagate-levelnetlist

In this stage, a technology-specific netlist appropriate forASICanalysisiscreatedfromthehigh-levelRTLdesign.

3.4 Timing, Area, and Power Analysis Using OpenROAD

Toestimateimportantperformancemetrics,OpenROAD wasusedforadditionalanalysisofthegeneratedgate-level netlist. A specified clock period was used to apply timing constraints,andthedesignwasconnectedtothematching standard cell libraries. The metrics listed below were obtained:

 Area: Estimated based on the total standard cell utilization

 Delay:Evaluatedusingstatictiminganalysis(STA)

 Power:Estimatedusingswitchingactivityandcelllevelpowermodels

Without complete physical implementation, this step offersaroughassessmentofthedesigninanASICcontext.

3.5 Methodology Significance

Thesuggestedmethodologyallowsforathorough assessment of the MLG-based MAC architecture by integrating FPGA and ASIC processes. While the ASIC synthesisandanalysisofferagreaterunderstandingofarea, latency,andpowercharacteristics,theFPGAsynthesissheds light on resource utilization and functional behavior. This dual-flow technique guarantees that the design is both practicallyfeasibleforhardwarerealizationandfunctionally correct.

4. Results

BothFPGA andASICdesignflowswereusedtoassessthe performance of the suggested Majority Logic Gate (MLG)based MAC architectures. The analysis focuses on area, latency, and power for ASIC synthesis and resource utilization,timing,andpowerforFPGAimplementation.

4.1 FPGA Results

Table -2: FPGAPerformanceComparisonof MLG-BasedMACUnits

Table 2 displays the FPGA performance of the suggested MLG-basedMACdevices.The4x4MACuses26 LUTs,butthe8x8MACneeds93LUTs,demonstratingthe anticipatedriseinresourceusewithscaling.

The suggested design exhibits better timing performance since its delay is much lower than that of the reference designs. Both architectures exhibit efficient power behavior despite increased complexity, with power consumption remaining almost constant at 0.11 W.

Overall, the FPGA results show that the suggested architecture achieves constant power consumption, competitive resource usage, and improved delay performance.

4.2 ASIC Results

Table -3: ASICPerformanceComparisonofMLGBasedMACUnits

Table 3 displays the ASIC performance of the suggested MLG-based MAC devices. The expansion of the

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

multiplier and reduction network causes the area to expandfrom997µm² for the 4×4 MAC to 5762 µm² for the8×8MAC.

Asthedesigngrows,thelatencyrisesfrom3.35nsto6.50 ns,representingthelongercriticalpath.Duetoincreasing hardware complexity and switching activity, power consumptionalsoincreasesfrom107µWto365µW.

ThesuggestedarchitectureoperatesinSky130(130nm) technologyandshowscompetitivepowerperformancewhen comparedtothereferencedesign.Variationsintechnology nodeanddesignprocesshaveanimpactondifferencesin delayandarea.

Overall,theASICfindingsverifythatthesuggesteddesign maintains a balanced trade-off betweenarea, latency, and powerwhilescalingpredictably.

5. CONCLUSIONS

This effort involved the design, synthesis, and evaluationof4x4and8x8MajorityLogicGate(MLG)-based Multiply-Accumulate (MAC) units. While maintaining traditional logic for partial product creation to guarantee accuracy,thesuggestedarchitectureincorporatesMLGinthe arithmetic phase, specifically in full adders and the multiplierreductionpath.BothFPGAandASICflowswere used to validate the designs. While ASIC synthesis using Yosys withSky130libraries andanalysiswith OpenROAD permitted examination of area, delay, and power characteristics,FPGAsynthesisusingXilinxVivadoverified correct functionality and offered insights into resource consumption, delay, and power. The results demonstrate thattheproposedarchitecturescaleseffectivelyfrom4×4to 8×8, with predictable increases in area, delay, and power. The use of MLG-based arithmetic contributes to efficient designwithcontrolledpowerbehavior.

Futureworkmayfocusonextendingthedesignto higherbit-widthMACunits,optimizingthearchitecturefor advancedtechnologynodes,andexploringtheuseofMLGin approximateorlow-powercomputingapplications.

REFERENCES

[1] H.Xiaoetal.,"FastandHigh-AccuracyApproximateMAC Unit Design for CNN Computing," in IEEE Embedded SystemsLetters(Volume:14,Issue:3,September2022)

[2] G.Rashmi,P.SharmilaRani,S.NagiReddy.,“MAJORITY LOGICIMPLEMENTATIONOFMACUNIT“inJETIR.ORG (2018JETIRJuly2018,Volume5,Issue7)

[3] Ku. Shweta N. Yengade, Associate Prof. P. R. Indurkar "Review On Design Of Low Power Multiply And AccumulateUnitUsingBaugh-WooleyBasedMultiplier" -inirjet.net(Volume:04Issue:02|Feb-2017)

[4] V. Gupta et al., "Approximate Computing: A Survey," IEEEDesign&Test,2013.

[5] A.Momenietal.,"DesignandAnalysisofApproximate CompressorsforMultiplication,"IEEETransactionson Computers,2015.

[6] S.S. Sabet etal.,"ANovel Majority-BasedCompressor for VLSI Applications," Microprocessors and Microsystems,2020.

[7] S. Mittal, "A Survey of Techniques for Approximate Computing,"ACMComputingSurveys,2016.

[8] O. Akbari et al., "Dual-Quality 4:2 Compressors for Dynamic Accuracy Configurable Multipliers," IEEE TransactionsonVLSISystems,2017.

[9] M.R.Tahaeietal.,"ALow-PowerandHigh-Performance Approximate Multiplier Using Majority-Based Logic," JournalofLowPowerElectronics,2021.

[10]XilinxInc.,"VivadoDesignSuiteUserGuide:Synthesis (UG901),"2022.

[11]A. G. M. et al., "Energy-Efficient Hybrid Accuracy CNN AcceleratoronFPGA,"IEEETransactionsonComputers, 2020.

[12]C.-H.Linetal.,"HighAccuracyApproximateMultiplier withErrorCorrection,"Proc.ofICCD,2013.

[13]Design of Efficient Quantum-Dot Cellular Automata (QCA)MACUnitin201830thInternationalConference onMicroelectronics(ICM)

[14]T. Zhang, W. Liu, E. McLarnon, M. O’Neill and F. Lombardi, “Design of majority logic (ML) based approximate full adders,” in Proc. IEEE Int. Symp. CircuitsSyst.,,pp.1-5,2018

[15]M. H. Moaiyeri, F. Sabetzadeh, and S. Angizi, “An efficient majority based compressor for approximate computinginthenanoera,”Microsyst.Technol.,vol.4, pp.1-13,2017.

[16]W.Liu,T.Zhang,E.McLarnon,M.O’Neill,P. Montuschi andF.Lombardi,“Designandanalysisofmajoritylogic based approximate adders and multipliers,” IEEE Trans.Emerg.Top.Comput.,2019.

[17]C. Labrado, H. Thapliyal and F. Lombardi, “Design of majority logic based approximate arithmetic circuits,” inProc.IEEEInt.Symp.CircuitsSyst., pp.2122-2125,2017.

[18]H. Jiang, F. J. H. Santiago, H. Mo, L. Liu, and J. Han, “Approximate arithmetic circuits: a survey, characterization and recent applications,” Proc. IEEE, vol.108,no.12,pp.2108-2135,2020.

[19]K.Navi,O.Kavehei,M.Rouholamini,A.Sahafi,and S. Mehrabi, “A Novel Majority- Based Full Adder,” MicroelectronicsJournal,Elsevier,vol.40,no.1, pp.126–130,2009.

[20]Y. Choi, “Parallel Prefix Adder Design,” Proceedingsof theIEEESymposiumonComputerArithmetic,pp.90–98,2005.

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

BIOGRAPHIES

Ms. Haritha Lakshmi B

Final Year B. Tech student in the Electronics & Communication Technology Department,SriVasavi EngineeringCollege, Tadepalligudem,WestGodavari, AndhraPradesh,India

Mr. Dinesh Vardhan D

Final Year B. Tech student in the Electronics & Communication Technology Department,SriVasavi EngineeringCollege, Tadepalligudem,WestGodavari, AndhraPradesh,India

Ms. Padma Sarojini P

Final Year B. Tech student in the Electronics & Communication Technology Department,SriVasavi EngineeringCollege, Tadepalligudem,WestGodavari, AndhraPradesh,India

Mr. Ashwin Vaibhav Datta K

Final Year B. Tech student in the Electronics & Communication Technology Department,SriVasavi EngineeringCollege, Tadepalligudem,WestGodavari, AndhraPradesh,India

Mr. M. K. S. Krishna Adithya

Final Year B. Tech student in the Electronics & Communication Technology Department,SriVasavi EngineeringCollege, Tadepalligudem,WestGodavari, AndhraPradesh,India

Mr. Punnam Nagaraju

Completed his M. Tech in 2013 fromJNTUK,Hyderabad.Hehas totally 11 Years of teaching experience. Presently he is workingasAssistantProfessorin theDepartment,SriVasavi EngineeringCollege, Tadepalligudem,WestGodavari, Andhra Pradesh, India. His interested Research area is Microwaveandmmwavefilters.