DESIGN AND IMPLEMENTATION OF 8T SRAM-BASED IN MEMORY MULTIPLY-ACCUMULATE OPERATIONS AND HAMMING DIST

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

DESIGN AND

IMPLEMENTATION

OF

8T

SRAM-BASED IN MEMORY MULTIPLY-ACCUMULATE OPERATIONS AND HAMMING DISTANCE CALCULATION

Prof.

P. V Sridevi M.E, PhD1 , Nagulakonda Achyut Sai2, Nakka Sravya Sri3, Nelli Preethika4 , Gilson Durao Nunes5

1HOD, Department of Electronics And Communication Engineering, Andhra University College of Engineering(A), Andhra Pradesh, India 2,3,4,5(Students, Department of Electronics And Communication Engineering), Andhra University College of Engineering(A), Andhra Pradesh, India

Abstract - This paper presents the design and implementation ofan8T SRAMbasedinmemorycomputing architecture for performing multiplyaccumulate operations and Hamming distance computation along with logic functionality. Conventional computing systems suffer from high latency and power consumption due to continuous data transfer between processor and memory. To overcome this limitation, the proposed approach performs computation directly within the memory array. An 8 by 8 arrayof8TSRAMcellsisdesignedwherethedecoupledread path ensures improved stability and enables simultaneous multi row activation. The computation is achieved through read bit line discharge, where the voltage variation represents the accumulation of bit level operations. The MAC result represents the number of zero bits, which is further used to implement logic operations such as AND, NOR, XOR and XNOR efficiently. Hamming distance is computed by interpreting bit differences using the same framework. The design is implemented and validated in a scematic capture tool Xschem using circuit level simulations in spice simulator Ngspice with Skywater 130nm technology PDK. The results demonstrate accurate operation with reduced hardware complexity and improved efficiency, making the proposed architecture suitable for low power and high performance in memory computing applications.

Key Words: In-Memory Computing, 8T SRAM, Multiply Accumulate (MAC), Hamming Distance, MAC based Logical operations, SRAM-Based Computing Architecture

1.INTRODUCTION

Moderncomputingsystemsarebasedontheconventional vonNeumannarchitecture,wherememoryandprocessing unitsarephysicallyseparated.Insuchsystems,data must be continuously transferred between the processor and memory, resulting in increased latency and power consumption. This limitation is commonly referred to as thevonNeumannbottleneckandbecomesmoreseverein data-intensive applications such as artificial intelligence andsignalprocessing.

To overcome this limitation, in-memory computing (IMC) has emerged as a promising approach in which computation is performed directly within the memory array. By reducing data movement, IMC significantly improves speed and energy efficiency while enabling parallelprocessing.

Static Random Access Memory (SRAM) is widely used for implementing IMC due to its fast access time and compatibility with CMOS technology. However, conventional 6T SRAM cells suffer from read disturbance issues, making them unsuitable for computation-based operations. To address this, the 8T SRAM cell is used, which provides a separate read path and improved stability.

In this work, an 8T SRAM-based in-memory computing architecture is proposed to perform multiply accumulate operations and Hamming distance calculation. The design utilizes read bit line discharge for computation and employs a simplified decoding scheme using comparators andpriorityencoders.Theproposedapproachalsoenables efficient implementation of logic operations directly withinthememory.

2. PROPOSED ARCHITECTURE

2.1

8T SRAM Cell

The8TSRAMcellconsistsofeighttransistors,includinga standard 6T storage core and two additional transistors formingaseparatereadpath.Thisseparationensuresthat the stored data is not disturbed during read operations whichisimportantasmultiplewordlineswillbeactivated anddatain6TSRAMcellmayflip.

The read operation is performed through the Read Word Line (RWL) and Read Bit Line (RBL), while the write operation is carried out using the Write Word Line (WL) andbitlines(BL.BLB).

2.2 SRAM Array Design

An 8×8 SRAM array is implemented, consisting of 64 memory cells. Each row represents an 8-bit word, and all

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

columnssharecommon bit lines. A 3:8decoder isused to selectarowtoreadorwrite.

Duringoperation:

 RBLissettoalowvoltage

 Multiplerowsareactivatedsimultaneously

 Parallelcomputationisachieved This structure enables efficient in-memory processing by allowing multiple cells to contribute to computation simultaneously.

2.3 Voltage decoder

TheVoltagedecodercircuitisusedtoconverttheReadBit Line(RBL) voltage values to digital outputs. It has of eight voltage comparators. The voltage threshold of each comparator is set according to the RBL voltage corresponding to each MAC count result. The comparator 3stages:preamplifierstage,regenerationstageand latch stage. It consists of double tail comparator(Fig. 3) for preamplifier and regeneration stages. RS latch(Fig. 4) is usedforlatchstage

The analog RBL voltage is converted into digital form by comparator These comparators classify the voltage into differentregionscorrespondingtoMACvalues. The RS latch captures the output and holds it constant until the next evaluation cycle. This ensures that the final MACoutputremainsconsistentacrossthecomputation.

Finally, a priority encoder generates the final digital MAC outputbyselectingthehighestvalidsignal.

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

2.4 MAC Operation using RBL

The multiply accumulate operation is performed on a coloumn using the capacitive behaviour of the Read Bit Line. Whenmultiplerowsareactivated,cellsstoringlogic ‘0’ create a charge path to 1.8V, causing a voltage rise on theRBL. Theamountofvoltageriseisproportional tothe number of active cells. In this design, the MAC output representsthe number of zeros presentinthearray.

For example MAC count of 5 means only five cells in the columnstorelogic‘0’.MACcountof8meansalleightcells in the column store logic ‘0’. MACcount of 0 means none of the cells store logic ‘0’ or all cells store logic ‘1’ in that column.

ATablerepresentingtherelationbetweennumberofzero storedcellsandMACvoltagesisshowninTable-1

Table -1: VariationofRBLVoltagewithMACCount Data in the row

Thecomputationprocessisasfollows:







Step1:RBLissetto0V

Step2:Multiplerowsareactivated

Step3:Cellsstoring‘0’chargeRBL

 Step4:Voltageriserepresentszerocount

Thisanalogrepresentationisthenconvertedintoa digital output.

3. IMPLEMENTATION OF LOGIC AND HAMMING DISTANCE

3.1 Logic Operations

The MAC output is represented using 9 lines (MAC0 to MAC8),whereonlyonelineisactiveatatimebasedonthe number of zeros. Logic operations can be realised with specificMACcountvalues

 MAC0→allbitsare1

 MAC8→allbitsare0

Logicoperationsarerealisedasfollows:

 ANDoperation:ActivatedwhenMAC0ishigh

 NORoperation:ActivatedwhenMAC8ishigh

ForXORoperation:

 Outputdependsonparity

 Evennumberofzeros→outputis0

 Oddnumberofzeros→outputis1 XNORisthecomplementofXOR.

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

3.2 Hamming Distance Computation

Hamming distance representsthe number of bit positions where two binary inputs differ. In this design, Hamming distance is computed using XOR-based comparison using MAC 1 outputs of all columns We load the two operands in1st and2nd rows.Wesetallotherrowstologic‘1’

Eachbitcomparisonproduces:

 1→ifbitsaredifferent

 0→ifbitsaresame

TheXORresultinstoredinseparaterowandMACcountof therowisdetermined.Inthefig8,ROW_HAMisextrarow forstoringXORresultoftheoperands.

The total number of differences is obtained using MAC operation within that row. Thus, Hamming distance is computedefficientlywithouttransferringdataoutsidethe memory.

4. RESULTS AND DISCUSSION

The proposed design is implemented using schematic capture tool Xschem and simulated with spice simulator NGSPICE with Skywater 130nm technology PDK. The simulation results verify the correct operation of the SRAMarray,MACcomputation,andlogicimplementation.

The RBL waveform shows a proportional voltage drop based on the number of active cells. The comparator successfully detects voltage levels and produces accurate digitaloutputs.

The MAC decoder correctly activates one of the output lines (MAC0–MAC8), which is further used to implement logic operations. XOR, XNOR, AND, and NOR operations areverifiedusingsimulationresults.

The proposed design demonstrates efficient computation withreducedhardwarecomplexityalongwithlogic-based decoding.

5. CONCLUSION

This paper presents an 8T SRAM-based in-memory computing architecture for performing multiply accumulate operations, logic operations and Hamming distance computation. The design utilizes RBL charging behavior for computation and employs a decoding approach using comparator and priority encoder Every logic function in the proposed design is derived from a single MAC computation. This helps minimize both chip area and power usage, making the approach well-suited foredgeAIapplications.

The proposed system reduces data movement, improves parallel processing capability, and minimizes hardware complexity. The simulated results in 130nm process confirm correct operation and demonstrate the effectiveness of the design for low power and high performancein-memorycomputingapplications.

ACKNOWLEDGEMENT

The authors would like to express their sincere gratitude to the Department of Electronics and Communication Engineering,AndhraUniversityCollegeofEngineering,for providingguidanceandsupportthroughouttheproject.

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International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

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