International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 13 Issue: 06 | Jun 2026
p-ISSN: 2395-0072
www.irjet.net
Design and Implementation of 32-bit RISC-V Processor with FloatingPoint Coprocessor and Clock Gating Optimization 1Bhagyalakshmi Chinivalar, 2Dr M S Suma 1MTech Student, 2Professor, Dept of ECE,BMS College of Engineering, Bengaluru, India.
-----------------------------------------------------------------------------***-------------------------------------------------------------------------project presents the design and stages Instruction Fetch (IF), Instruction Decode (ID), implementation of a 32-bit RISC-V processor integrated with Execute (EX), Memory Access (MEM), and Write Back a dedicated Floating-Point Coprocessor for high-performance (WB)—allow multiple instructions to be processed in floating-point computation. The core processor is based on parallel, improving overall performance. The final design the RV32I instruction set architecture, while the floating- is implemented in Verilog HDL and tested using simulation point operations are offloaded to a separate IEEE-754 and synthesis in the Vivado design environment, making it compliant Floating-Point Coprocessor, enabling efficient suitable for deployment on FPGA platforms. This processor demonstrates improved performance in mixed-precision computing. The architecture employs a design applications involving real-time signal processing, data tightly coupled coprocessor interface that allows the main RISC-V core to dispatch floating-point instructions to the analysis, and embedded intelligent systems, while coprocessor and handle data exchange through dedicated maintaining the modularity and openness of the RISC-V registers and control signals. This modular approach architecture. provides better hardware separation, improved scalability, II. LITERATURE SURVEY and easier maintenance compared to a unified execution unit. The design includes optimized modules for instruction fetch, A rigorous review of contemporary architectural decode, register file, integer ALU, control unit, hazard exploration establishes the technical contextual baseline detection, and pipeline management in the main core, along for this study: with a complete floating-point coprocessor consisting of FP1) Banna Saif et al.: Implemented an FPGA-based ALU, floating-point register file, and coprocessor control educational RISC-V processor (RV32I) with a simple logic. The entire system is implemented in Verilog HDL. It has pipeline, emphasizing simplicity and hands-on learning been simulated, synthesized, and tested on an FPGA platform for embedded applications. This addresses accessible softusing the Vivado design suite. Pipeline hazards are effectively core configurations for basic controls but lacks singlemanaged using forwarding, stalling, and hazard detection precision numeric arithmetic acceleration networks. techniques to ensure smooth operation between the main 2) Saussereau et al.: Proposed AsteRISC, a size-optimized processor and the floating-point coprocessor. Experimental RISC-V core for design-space exploration, focusing on results demonstrate significant performance gains in minimal area and efficient resource usage. The core floating-point intensive workloads while maintaining low focuses heavily on optimizing area footprints, establishing resource utilization on the FPGA. The proposed design offers structural benchmarks for resource-constrained layouts at an excellent balance between performance, flexibility, and the cost of execution performance for data-intensive hardware cost, making it highly suitable for embedded calculations. systems, IoT devices, signal processing, and other mixed integer-floating-point applications. 3) Thanga Dharsni et al.: Presented a hazard-free pipelined RV32I RISC-V architecture, ensuring correct Keywords-RISC-V, Coprocessor, IEEE-754, Clock Gating, instruction execution without stalls for improved FPGA, Verilog HDL, Vivado. performance. Their techniques rely on optimized forwarding logic, minimizing structural bubbles across basic mathematical workflows. I. INTRODUCTION
Abstract-This
4) Phangestu et al.: Implemented a five-stage pipelined 32-bit RISC-V soft processor in VHDL, supporting modular, FPGA-compatible educational and research applications, laying out classical instruction overlapping conventions.
The RISC-V architecture is an open-source Instruction Set Architecture (ISA) that is widely used in academics, research, and industry due to its flexibility, simplicity, and free licensing model. Unlike traditional proprietary processor architectures, RISC-V allows designers to modify, extend, and optimize the processor based on application needs. This makes it an ideal platform for designing custom processors for embedded systems, digital signal processing, and machine learning applications. In this project, a RISC-V 5-stage pipelined processor is designed and implemented using Verilog HDL and synthesized on Xilinx Vivado. The five pipeline
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5) Gupta et al.: Designed a high-speed, resource-efficient UART for reliable serial communication, suitable for peripheral integration with embedded processors like RISC-V, defining high-frequency clock divider methodologies.
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