International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 12 Issue: 10 | Oct 2025
p-ISSN: 2395-0072
www.irjet.net
Design and Comparative Analysis of Dynamic Threshold MOSFET and Sleep Transistor Configuration Based 7T SRAM Cell Nikhil Saini1, Naman Garg2, Dr. N.P. Singh3 1
M.Tech, Embedded System Design, School of VLSI Design and Embedded Systems, National Institute of Technology, Kurukshetra, Haryana, India
2
B.Tech, Electronics and Communication Engineering, National Institute of Technology, Kurukshetra, Haryana, India 3
Associate Professor, Electronics and Communication Engineering Department, National Institute of Technology, Kurukshetra, Haryana, India *** Abstract – Power dissipation in Static Random Access Memory (SRAM) cells has emerged as a critical design challenge with continued technology scaling into the nanometer regime. This paper presents a comprehensive comparative analysis of power reduction techniques for 7-Transistor (7T) SRAM cells, investigating five distinct configurations: basic 7T SRAM, Sleep Transistor, Dynamic Threshold MOSFET (DTMOS), DTMOS with Sleep Transistor, and Stack Transistor with Sleep Transistor. All designs are simulated using 90nm Predictive Technology Model (PTM) in LTSpice XVII at 300mV subthreshold supply voltage. Performance evaluation encompasses four critical metrics: power dissipation, propagation delay, Power Delay Product (PDP), and Energy Delay Product (EDP). Simulation results demonstrate that DTMOS combined with Sleep Transistor achieves optimal power-performance balance with 63.5% power reduction (333.83pW) and minimal propagation delay (3.84ps), yielding bestin-class PDP of 1.28fJ and EDP of 4.9aJ·s. Alternatively, Stack with Sleep configuration delivers maximum power savings of 70.4% (270.72pW) at the cost of increased delay (12.31ps), making it suitable for ultra-low-power applications with relaxed timing constraints. This comprehensive study establishes practical design guidelines for selecting appropriate low-power techniques based on application-specific power- performance requirements in battery-operated mobile devices, IoT systems, and wearable electronics.
Key Words: 7T SRAM, DTMOS, Sleep Transistor, Transistor Stacking, Power Gating, MTCMOS, Low Power VLSI, Leakage Reduction, Subthreshold Operation, Energy Delay Product
1. INTRODUCTION Static Random-Access Memory (SRAM) occupies a pivotal role in modern VLSI systems, serving as high-speed cache memory in microprocessors, system-on-chip (SoC) designs, and embedded computing platforms. With aggressive technology scaling into the sub-100nm regime, SRAM arrays typically constitute 60–90% of total chip area in contemporary processors, making their power optimization paramount for overall system energy efficiency [1][11]. The International Technology Roadmap for Semiconductors (ITRS) identifies SRAM leakage power as one of the most criti- cal challenges facing next-generation integrated circuit design. Power dissipation in SRAM cells comprises two principal components: dynamic power consumed during read/write operations, and static (leakage) power dissipated during standby mode. As CMOS technology scales below 90nm, several phenomena contribute to exponential growth in leakage current: (i) reduced threshold voltage (Vth) to maintain acceptable drive current at lower supply voltages; (ii) thinner gate oxide resulting in increased gate tunneling leakage; (iii) enhanced drain-induced barrier lowering (DIBL) and subthreshold swing degradation; and (iv) elevated junction leakage due to higher doping concentrations. Consequently, static power has evolved from a negligible component to often exceeding 40–50% of total chip power in advanced technology nodes [1][2]. 1.1 Motivation and Problem Statement The proliferation of battery-operated portable devices—including smartphones, tablets, wearable electronics, and Internet-of-Things (IoT) sensor nodes—has intensified the demand for ultra-low-power memory solutions. SRAM cells in these applications spend significant time in standby mode, where leakage power dominates energy consumption. Traditional 6T SRAM cells, while area-efficient, suffer from read stability issues at low voltages and exhibit substantial leakage currents. The 7T SRAM architecture, incorporating an additional transistor in the ground path, offers improved read stability and reduced read disturb noise, making it attractive for low-voltage operation.
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