International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 13 Issue: 05 | May 2026
p-ISSN: 2395-0072
www.irjet.net
A Comprehensive Review on Low-Power High-Speed XOR/XNOR Gate Design Techniques in VLSI Systems Sushila Panika1, Aditya Mishra2 1M.Tech Scholar, Department of Electronics & Communication Engg., VIST, Bhopal, Madhya Pradesh, India
2Assistant Professor, Department of Electronics & Communication Engg., VIST, Bhopal, Madhya Pradesh, India
---------------------------------------------------------------------***--------------------------------------------------------------------This review paper presents a detailed analysis of various Abstract – The rapid scaling of Very Large-Scale Integration (VLSI) technology has significantly increased the demand for energy-efficient and high-speed digital circuits. Among fundamental logic components, Exclusive-OR (XOR) and Exclusive-NOR (XNOR) gates play a critical role in arithmetic units, multipliers, and cryptographic systems. Their performance directly influences the overall efficiency of digital datapaths. Over the years, various design techniques such as static CMOS, pass-transistor logic, dynamic CMOS, hybrid logic, and multi-threshold CMOS (MTCMOS) have been proposed to optimize power consumption, delay, and area. However, each technique presents trade-offs in terms of leakage power, noise margin, and robustness. This paper presents a comprehensive review of existing XOR/XNOR gate design methodologies, analyzing their advantages, limitations, and performance characteristics. Furthermore, emerging approaches such as conditional keeper techniques, compute-in-memory architectures, and nanoscale devices are also discussed. Finally, key research gaps and future directions are identified to guide the development of next-generation ultra-low-power arithmetic circuits.
XOR/XNOR design techniques, highlighting their strengths, limitations, and suitability for modern VLSI systems.
Key Words: XOR/XNOR, VLSI, Dynamic CMOS, MTCMOS,
2.2 Pass Transistor Logic (PTL) Pass Transistor Logic (PTL) reduces the number of transistors by eliminating redundant PMOS devices and using transistors as switches to pass logic levels. This results in compact designs with reduced area and lower power consumption. Despite these advantages, PTL suffers from threshold voltage loss, which leads to degraded output voltage levels. This degradation affects noise margin and limits its applicability in cascaded logic circuits. Additionally, PTL designs face scalability issues in deep sub-micron technologies due to increased leakage currents.
2. CLASSIFICATION OF XOR/XNOR DESIGN TECHNIQUES XOR/XNOR gates can be broadly classified based on logic styles: 2.1 Static CMOS Logic Static CMOS logic is the most widely adopted design style due to its robustness and ability to provide full voltage swing at the output. It consists of complementary pull-up (PMOS) and pull-down (NMOS) networks, ensuring reliable operation under varying conditions. The primary advantage of static CMOS logic lies in its high noise immunity and stable operation, making it suitable for critical applications. However, XOR/XNOR implementations using static CMOS typically require around 16 transistors, leading to increased input capacitance and higher dynamic power consumption. As a result, this logic style is less efficient for high-speed and low-power applications.
Low Power Design, Hybrid Logic, PDP, Leakage Reduction 1. INTRODUCTION With continuous scaling in semiconductor technology, modern digital systems demand high-speed operation along with minimal power consumption. The breakdown of traditional scaling laws has led to increased leakage currents and thermal issues, making energy efficiency a critical design parameter. XOR and XNOR gates are fundamental building blocks in arithmetic circuits such as adders, multipliers, and cryptographic modules. These gates often lie on the critical path of computation, making their optimization essential for improving overall system performance.
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2.3 Dynamic CMOS Logic Dynamic CMOS logic operates using two phases: precharge and evaluation, controlled by a clock signal. During the precharge phase, the output node is charged to a known
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