In this paper the low-power and high-speed design approach of one Complementary Metal Oxide Semiconductor
(CMOS) circuit based on NAND function has been reported. The CMOS design methodology has been followed to construct the
circuit. The design has been carried out at 150 nm channel length of Metal Oxide Semiconductor (MOS) transistor. Average
power consumption and gate delay of the circuit has been measured. Power-delay product (PDP) of the circuit has been
calculated for optimized operation. The simulation of the circuit has been carried out with the help of Tanner SPICE (T-SPICE)
software.
