This study focuses on the development of high-speed adder circuits utilising the Hardware Description Language
(HDL) within the Xilinx ISE 9.2i platform, as well as their implementation on Field Programmable Gate Arrays (FPGAs) to
analyse planning parameters. The main building component of the Arithmetic Logic Unit (ALU) is the adder, and hence the
performance of the Control Processing Unit is determined by it (CPU). The ALU and the register file are the two primary
components of processors. The carry-chain extra operation could be one of the important channels within an ALU. In this
paper, we've simulated and synthesised a variety of adders in order to find the most efficient one.
