Functional verification mainly based on coverage driven constraint. The universal memory controller is aiming
to advance the performance of the prevailing memory controllers through a complete integration of the all memory in
addition of providing novel features. It mainly serves as one amongst the basic important feature that’s lagging in most of
memory controller that is power being consumed. The aim of the paper is to validate the design and to generate regression
test cases in the test-bench in order to obtain 100% functional coverage using System Verilog (SV) and a typical code
coverage
