This proposal improves the productivity of the preparation components when managing numerous check interpretations
in the middle of domains. The proposed engineering enables the framework to be adapted to any type of FPGA gadget and is also
suitable for multicode devices. The chip away from the RM- Net to Mp-Soc Platform could be reached for additional devices
approved in the Xlinx. The proposed structure would assist in the development of at least one module within a single FPGA device
that will enable the use of different tasks applications. This work builds and updates a powerful VHDL engineering Mp-Soc based
Reconfigurable Multi-Clock Ring Net. This concept allows the NOC to adapt number of modules within one FPGA device
through integrating in an architecture.
