The efficiency of bus architecture is an important factor. The performance of an on-chip interconnection architecture,
which is used for communication between the functional blocks, depends on the efficiency. The low cost, efficient bus
architecture is determined by various factors such as improved width of the bus, more data transfer cycle, a faster clock speed of
the bus, and throughput. This paper presents a survey on APB bus architecture and Wishbone bus architecture and a
comparison between them. It starts with the introduction and features of the APB bus architecture followed by the introduction
to Wishbone bus Architecture and its features and concludes with a comparison between them. The Wishbone Bus Architecture
is developed by the Silicore Corporation appears to have more special performance parameters such as additional data transfer
cycle (Read-Modify-Write cycle) and the use of a flexible arbitration scheme. It also has an advantage that its IP cores do not
require registration.
