The power used by digital integrated circuits has become a key restriction for design and development of VLSI as the
device complexity and transistor density increase. Clock-gate synthesis methods are applied to circuits to prune changes in
registers by modifying the next-state register functions in order to reduce complex power dissipations. Therefore, sequential
inspection of the clock-guided circuits (SEC) is needed for testing this form of synthesis. A new design to rising the efficiency of
network-on-chip buffers is being proposed. The non-uniform use of buffers in the network is leveraged and control is used in
unusual buffers. A part of the buffer is turned on instead of shutting down the buffer completely. There is a significant
performance gain when preferring setup, since the buffer will accept network packages. According to the growing need for better
reliability with low energy consumption, scaling up of CMOS technology continued.
