Ternary content addressable memory (TCAM) is a high performance search engine which accesses the data based on
its contents in a single clock cycle. To reduce the power consumption of the TCAM cell when we search the data. Most memory
devices store and retrieve data by addressing specific memory location. As a result this path often becomes the limiting factor for
the systems that rely on fast memory access. In this paper to design six transistors based SRAM design with eight transistors of
two side self gating TCAM and to design four transistors using transmission gate logic function of XOR based TCAM. This
design is to increase the matched line search process and to reduce the overall dynamic power consumption level of TCAM array
design. Our proposed work is to design CMOS based RAM and Ternary CAM memory architecture. This design is used to find
matched line data effectively and to reduce the leakage power level for match line searching process
