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GRD Journals | Global Research and Development Journal for Engineering | International Conference on Innovations in Engineering and Technology (ICIET) - 2016 | July 2016

e-ISSN: 2455-5703

A Low Power Memory Architecture for ZigBee Trans-Receiver 1M.

Marudhupandian 2V. Kamalkumar 1 Department of Information and Communication Engineering 2Department of Electrical and Electronics Engineering 1,2 KIT- KalaignarKarunanidhi Institute of Technology, Coimbatore-641 402 Abstract A Low-power memory architecture for Zigbee Trans-Receiver is designed in this project. It proposes a level converting Retention flip-flop (RFF) in dual edge triggered pulse with feedback system in Zigbee SoCâ€™s Trans-receiver. This RFF the master flip flop are hold the data in standby mode and the data will be restored in the slave flip flop in active mode thus reduces the power consumption. Then the data will be passed from the VDD, Coreto and VDD, IO with the help of NMOS passTransistor. This proposed RFF does not require any additional control signals for power and data transitioning. This RFF with dual-edge triggered pulse with feedback system will overcome the problems like high power consumption, large DC current and low performance when compared with existing single-edge triggered RFF. Using 180nm technology the proposed RFF is designed for low power consumption using Tanner EDA Tool. Keyword- I/O supply voltage, Retention Flip flop, Standby leakage current, Standby mode, Level-Conversion, Dual-Edge triggered flip-flop __________________________________________________________________________________________________

I. INTRODUCTION In Recent years, wireless sensor networks have been evolved at an accelerated space. The WSNs to build a Zigbee protocol (10), in which medium access control and physical layer are defined by IEEE 802.15.4 (2) has been generally used, because this protocol has low data rate, low power consumption and long battery life. This features to makes a Zigbee protocol preferred over other technologies like as Wi-Fi and Bluetooth (9). In addition most Zigbee systems-on-chips(SoCs) supports a number of power modes including standby mode that time to maximize the battery life (3) up to 99.09%.Thus, standby power reduction is very important to minimize the power consumption of Zigbee SoCs. The power consumption is more critical mean the leakage current increases exponentially with their threshold voltage ( ). The power returning the standby mode Zigbee SoCs (8) can operates properly, the logic states of hardware calibration, configuration and network information should be preserved before entering the standby mode and also data will betransfer between standby mode and active mode with low power consumption. This RFF are widely used many Zigbee SoCs (8) for storing the data and different types of RFF have been researched. The remainder of this paper is organized as follows. The Existing RFFs is compared with the proposed RFF, and experimental results are presented in Section II. Experimental results of existing and proposed system in section III. Finally conclude and future work with References in Section IV.

II. RETENTION FLIP â€“FLOPS A. Existing Level-Converting RFF The Existing level-converting RFF is shown in Fig. 2. The RFF is also based on a cross-coupled-inverter latch as the DFF, and an additional data transmission path (M3 and M1). The transistors are used, and the core and retention logic are suppliedby VDD, CoreandVDD, IOrespectively. Level conversionfromthe VDD, Coren in the master latch to the VDD, IO in the slave latch is achieved through an NMOS transistor. The proposed RFF operates as follows (Fig 2). When give the data in the master latch are high and low, respectively, an access transistor M4 (or M3) is turned on andanother access transistor M3 (or M4) is turned off. Then, the ON-state access transistor M4 (M3) forms atransmission path between the master latch and the slave latch but this RFF operates on only single edge triggered clock pulse. In other words, only the transmission path from the master latch to the slave latch is determined on the basis of the state of datainthemaster latch, and the voltage level can be converted in The slave latch without generating a dc-current path because only a low signal is transmitted at all times. Thus theVDD, Coredomain is converted into the VDD, IO domain without the need for an additional level-up converter. Level-down conversion from VDD, IOto VDD, Coreoccurs at INV3 and INV4, which are composed of thick-oxide transistors but supplied by VDD, Corein the standby mode,

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Fig. 1: Block Diagram of existing system

When RSTb is asserted low, CK becomes low, and is collapsed by turning off the voltage regulator; in this case, the slave latch is isolated by turning off the access transistors (M1 and M2) and operates as a retention latch to hold logic states by VDD, IOthat is always turned on. The write operation is performed by pulling down slv_left or slv_right in Fig. 2 because the master latch always transmits a low signal to the slave latch in the proposed RFF.

Fig. 2: Schematic of existing system

The pull-down network of slv_right (slv_left) consists ofM1 and M3 (M2 and M4) and the nMOS in INV6 (INV5).However, the pull-up network of slv_right (slv_left) composed of two-stacked pMOS transistors in INV2 (INV1) is simultaneously turned on if the data to be transferred is different than the retained data. However, the speed degradation is not a problem in this target application because the digital logic in ZigBee SoCs operates at a low frequency of approximately 20-100 MHz Thus, the proposed RFF can be appropriately applied to the ZigBee SoCâ€™s and also implemented using 180nm Technology. B. Proposed Retention Flip-flop The Block Diagram of proposed Retention flip flop (RFF) for Dual-edge triggered pulse with feedback system shows that figure 3. This RFF used to hold the data in standby mode and restore the data in active mode. It consists of Master flip flop (TG, Inverter, pMOS/nMOS Transistor) and Slave flip flop (Memory, Retention logic), is connected to series with feedback circuit through buffer, it acts as both positive and negative clock pulses to reduce the some parameters such as power consumption, leakage current reduction and increase the performance compared to existing singleâ€“edge pulse triggered Retention flip flop (RFF). Fig.4 shows that the schematic diagram of proposed RFF consists of 5 inverters, 4 NMOS pass transistors, 2 Transmission gate and dual inverter. The input of the proposed system to given the transmission gates namely TG1, and TG2 or analog switch, is defined as an electronic element that will selectively obstruct or pass a signal from the input to the output. This solid-state switch is made up of a pMOS transistor and nMOS transistor. The control gates are based on a complementary manner so that both transistors are either ON or OFF. This transmission gate is used to pass the original and complements value to the master flip flop with the help of inverters (INV1 and INV2).

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A Low Power Memory Architecture for ZigBee Trans-Receiver (GRDJE / CONFERENCE / ICIET - 2016 / 044)

This RFF needs 5 inverters namely INV1, INV2, INV3, INV4, and dual inverter. The output of the TG1 to give the input of INV1 and this output is given to the input of INV2 are used to pass the data to master flip flop for obtaining original and complement values. The inverter output will pass the NMOS pass transistor. Here INV 2 (or INV1) input and output of the master latch is high and low respectively, an access transistor M4 (or M3) is turned on, and another access transistor M3 (or M4) is turned off. Then, the ON-state access transistor M4 (M3) forms a transmission path between the master latch and the slave latch, and INV 2 I/O becomes an input of the transmission path. This master flip flop is used to hold the data in standby mode. The output of the NMOS pass transistor is given to the dual inverter in the slave flip flop. Slave flip flop contains cross-coupled structure of dual inverter. It is act as an opposite for normal inverter because the dual inverter is used to transmit the same input value to the output side with storage elements. This salve flip flop is used to restore the data in active mode.

Fig. 3: Block diagram of proposed RFF

In addition the dual inverter acts as retention logic in the idle mode.Both the MOS transistors are used for the Core and Retention logic is supplied by VDD, Coreand VDD, IO respectively. Level conversion from the VDD, Coredomain in the master flip flop to the VDD, IO domain in the slave flip flop is achieved through an NMOS pass-transistor. The level-conversion means basically it converts one voltage in to another voltage. Further reduction in the standby leakage current in master flip flop can be achieved by arranging the access transistors (M1 and M3, and M2 and M4) in a stacked structure, and the dual inverter in the slave flip flop are designed using stacked p/nMOS transistors, allowing the standby leakage current to also be reduced. Level down conversion from VDD, IO to VDD, Coreoccurs at INV3 and INV4, which are composed of thick-oxide transistors but supplied by VDD, Core. In the standby mode, when reset signal RSTb is asserted low, dual-CLK pulse becomes low; In this case, the slave flip flop is isolated by turning OFF the access transistors (M1 and M2) and operates as a retention latch to hold logic states by VDD, Corethat is always turned ON and also Dual-edge pulse triggered flip flop with feedback system input is connected to the data and feedback of output is connected input (Q) and complementary input (Qbar) through the buffer, because buffer is a temporary storage device for transferring the data with high speed between the input and output. This feedback circuit is used to slightly increase the delay and reduce power consumption. INV3 and INV4 are used to transmit the output of the system and its complement values.

Fig. 4: Schematic of proposed RFF

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A Low Power Memory Architecture for ZigBee Trans-Receiver (GRDJE / CONFERENCE / ICIET - 2016 / 044)

III. POWER COMPARISON &RESULTS The performance of the proposed RFF is evaluated by comparing the average power and delay for Existing RFF and proposed RFF. In general, a Power, delay based comparison is appropriate for low power portable systems in which the battery life is increasing the primary index of energy efficiency. The following from TABLE 1 furnished the performance parameters for attained minimum frequencies. Parameters

Average Power (watts)

Existing System 0.91708 Proposed System 0.00378 Table 1: Power and delay comparison

Delay (sec) 2.54 3.95

Table.1 shows that power and delay comparison of proposed system with existing system. The average power is 65% dramatically reduces and delay is 25% slightly increased when compared to existing RFF. This low power RFF of Zigbee based SoC’s Trans-Receiver is designed using Tanner EDA v13.0 180 nm Technology.

IV. CONCLUSION AND FUTURE WORK The Retention flip-flop (RFF) is commonly used technique for Memory requirements of various SoC’s applications. The Proposed RFF of dual-edge triggered flip flop with feedback system (DETFF) is operates on both positive and negative clock pulse. This RFF achieves hold the data in standby mode and retained data in the active mode, also adopting a power management scheme to use VDD, IOand VDD, Corefor data retention and to turn off the voltage regulator in the standby mode for reduced power consumption and delay in SoCs applications. In addition, the retention flip flop in the proposed RFF is composed of a stacked structure with thick-oxide transistors to reduce the standby leakage current. As validated in the simulations and experiments, the proposed RFF is highly suitable for deployment in low-power wireless sensor networks using the ZigBee protocol. The Future work is concentrated to design a Low-swing Signal Feed through Clocking Scheme for reducing the power consumption, delay and remove the glitches in the proposed RFF. The LC resonant clocking scheme is based on Low-swing Differential conditional capturing flip-flop (LS-DCCFF) used for Low Power applications such as Wireless Networks, Computing Techniques, Nano-Technology and industrial Applications etc.

REFERENCES [1] Hamid Mahmoodi-Meimand and Kaushik Roy(2004),“Dual-Edge Triggered Level Converting Flip Flops” School of Electrical and Computer Engineering, Purdue University West Lafayette, IN, USA.IEEE. [2] J. Hu, W. Liu, W. Khalil, and M. Ismail (2010), “Increasing sleep-mode efficiency by reducing battery current using a DCDC converter, "in Proc. IEEE Int. MWSCAS, Aug. [3] J.-S. Lee,Y.-W. Su, and C.-C. Shen (2007), “A comparative study of wireless protocols: Bluetooth, UWB, ZigBee, and WiFi,” IEEE Wireless Commun., vol. 14, no. 4, pp. 70–78, Nov. [4] J. Tschanz, et al (2001), “Comparative delay and energy of single edge triggered and dual edge-triggered pulsed flip-flops for high performance microprocessors,” International Symp. On Low Power Electronics and Design, pp. 147–152. [5] Jung-Hyun Park, Heechai Kang, Dong-Hoon Jung, Kyungho Ryu, and Seong-Ook Jung (2015), “Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs”, Senior Member, IEEE Transactions on VLSI Systems, Vol. 23, No. 3. [6] L. T. Clark, M. Kabir, and J. E. Knudsen (2007), “A low standby power flipflop with reduced circuit and control complexity,” in Proc. IEEE CICC,pp. 571–57. [7] N. B. Kothari, T. S. B. Sudarshan, S. Gurunarayanan, and R. A. Chandrasekhar (2006), “SoC design of a low power wireless sensor network node for ZigBee systems,” in Proc. Int. Conf. Adv. Comput. Commun.,pp. 462–466. [8] P. Zhao et al (2009), “Low-power clocked-pseudo-nMOS flip-flop for level conversion in dual supply systems,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 17, no. 9, pp. 1196–1202. [9] Ravi.T, Irudaya Praveen.D, Kannan.V (2013), “Design and Analysis of High Performance Double Edge Triggered D-Flip Flop”, (IJRTE) ISSN: 2277-3878, Volume-1, Issue-6. [10] W. Kluge et al (2006), “A fully integrated 2.4-GHz IEEE 802.15.4-compliant transceiver for ZigBee applications,” IEEE J. Solid-State Circuits,vol. 41, no. 12, pp. 2767–2775. [11] Xiaohui Fan, Yangbo Wu, Hengfeng Dong, and Jianping Hu (2014), “A Low Leakage Autonomous Data Retention FlipFlop with Power Gating Technique Faculty of Electrical Engineer and Computer Science and Technology, Ningbo University, Ningbo 15211, China.

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