Computer Architecture Course 320241jacobs University Bremen Novembe
Perform the following arithmetic operations by giving MIPS code: 1. a = b + c 2. a = b − c + d 3. a = 8 b 4. a = (2 + b) ·4 Please assume that a is in register $t0, b in register $s0, c is in register $s1 and d is in $s2.. Keep in mind that you do not know the mul operation yet. Also, comment each relevant code block.
Give binary codes of the MIPS instructions for the operations 1 and 2 of the previous problems.
Suppose you write the following C code: B[5] = A[2] + A[3]. Please write down the MIPS assembler code for this code. Assume that the address of base of A is stored in $s0, the base of B is stored in $s1. Comment the relevant code blocks.
Suppose you write the following C code: B[x] = A[x + 2] + A[x + 3]. Please write down the MIPS assembler code for this code. Assume that the address of base of A is stored in $s0, the base of B is stored in $s1, and the value of x in $t0. Comment the relevant code blocks.
The register instruction format for the instruction addi uses 6 bits for the opcode, 5 bits for the first register, 5 bits for the second register, and 16 bits for the constant value that is to be added. A detailed analysis of machine code has revealed that not more than 12 registers are needed for the processor and therefore it has been decided to reduce the number of general purpose registers to 16. How and why could the instruction format for the addi instruction be changed?
Paper For Above instruction
The assignment pertains to fundamental operations in MIPS assembly language programming and instruction set architecture design. It covers writing assembly code for simple arithmetic operations, understanding instruction binary encoding, handling memory accesses with arrays, and considering architectural modifications for instruction encoding.
First, the problem asks for MIPS assembly implementations of basic arithmetic expressions involving registers, with specific assumptions about register allocations, namely that the variable 'a' is stored in register $t0, and variables 'b', 'c', and 'd' are stored in $s0, $s1, and $s2, respectively. The operations include addition, subtraction, multiplication by a constant, and a compound operation involving addition and multiplication. Since the instruction set lacks a 'mul' instruction, repeated addition may be necessary, or multiplication simulated.
Next, the assignment requires translating some of these arithmetic expressions into their corresponding
binary machine code representations. This necessitates an understanding of the R-format and I-format instruction encodings in MIPS, and how to convert a given instruction into its binary form based on its opcode, source/destination register addresses, and immediate values.
The third part focuses on memory access operations for arrays. The task involves writing MIPS code to perform array element retrievals and modifications based on given C-like array indexing semantics. Comments should clarify each step, including address calculations via base addresses and offsets, usually scaled by element size (commonly 4 bytes for 32-bit integers).
In the subsequent question, the code involves memory operations with variable indices, requiring calculation of effective addresses based on a runtime index stored in a register. The assembly should compute the correct memory addresses dynamically and load or store array elements accordingly.
Finally, the problem discusses architecture-level modifications: specifically, how an instruction format could be adapted if the processor only needed 16 general purpose registers instead of 32. Adjustments to opcode and register fields could reduce instruction size, and such changes are motivated by the desire to optimize instruction encoding efficiency for a smaller register file.
Overall, this assignment explores key aspects of MIPS instruction set programming, machine code encoding, memory addressing, and architectural design considerations, essential for understanding low-level computer architecture and assembly language programming.
References
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Hardware/Software Interface (2nd ed.). Morgan Kaufmann.
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